Hypervisor linux cpuinfo update#
Intel xTPR update control: Can disable sending Task Priority messagesĮver wonder what these "power management" in x86 Linux's /proc/cpuinfo mean ? Intel Virtual NMI (Non-Maskable Interrupts)ĪMD eXtended OPeration instructions (was: SSE5)Įxtended topology enumeration CPUID leaf 0xb, as in arch/x86/kernel/cpu/topology.c Use unfair spinlock when running on hypervisorĪMD VMCB (Virtual Machine Control Block) clean bits support Time Stamp Counter is known to be reliableĪMD MST-based Time Stamp Counter scaling/rate control
RDTSC (Read Time Stamp Counter) instruction Intel TPR (Task Priority Register) Shadow AMD-V, V for Virtualization)ĪMD SYSCALL/SYSRET instructions (for fast system calls)ĪMD Trailing Bit Manipulation instruction
Intel Safer Mode eXtensions, part of the Intel Trusted eXecution Technology (TXT)ĪMD Secure Virtual Machine (i.e. Intel Supervisory Mode Execution Protection Intel SYSENTER/SYSEXIT instructions (for fast system calls)ĪMD SKINIT/STGI (Secure kernel init & jump with attestation/Set global interrupt flag) instructions Intel Haswell restricted transactional memory Page Global Enable: the global bit in the Page Directory Entries (PDE) & Page Table Entries (PTE) is supported The NOPL (0F 1F) instructions 21 available, was AMD_C1EĪMD SVM Next RIP Save: Save next sequential instruction pointer on Virtual Machine exitĪMD 1-GB large page support (PDPE=Page-directory-pointer entry)ĪMD Bulldozer (Family 15h) core performance counters Time Stamp Counter does not stop in C states swapping the high & low bits of a long value during a MOV) instruction (currently only available on Intel Atom processors) LAHF/SAHF (Load/Store Flags into AH Register) instruction in Long ModeĪMD LBR (Last Branch Record) Virtualization supportĪMD's misaligned accesses for SSE instructions Intel Haswell hardware lock elision (transactional memory support) Intel FS/GS Base registers access instructions, part of AVX Intel enhanced REP MOVSB/STOSB instructionsġ6-bit floating-point conversion instructionsĪMD flush-by-ASID (Address Space ID) supportĪMD 4-operand fused multiply-add instructions TPR: Task Priority Register) in 32-bit modeĭirect Cache Access (the ability to prefetch data from MMIO)ĬPL-qualified debug store (CPL=Current Privilege Level) Time Stamp Counter ticks at a constant rateĬR8 (Control Register #8, a.k.a. L1 Context ID: the L1 data cache can be set to adaptive or shared mode by the BIOSĬMOV (conditional move) instructions (plus FCMOVcc, FCOMI with FPU) The first group includes instructions such as ANDN, BEXTR, BLSI, BLSMK, BLSR, TZCNT, and the second group, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX.Ĭentaur MCRs (= MTRRs, Memory Type Range Registers) Intel 1st/2nd group advanced bit manipulation extensions. On-chip APIC (Advanced Programmable Interrupt Controller) XCRYPTxxx instructionsĪCPI (Advanced Configuration and Power Interface) via MSR (Model-Specific Register)ĪES (Advanced Encryption Standard) instructionsĪMD multi-node processor (DCM=Direct Connect Module)Īctual Performance Clock Counter (APERF) and Maximum Qualified Performance Clock Counter (MPERF) in MSRs
Here is the answer (from Linux kernel sourceĪMD Advanced Bit Manipulation instruction, i.e. Ever wonder what these "flags" in x86 Linux's /proc/cpuinfo mean ?
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